1. Field of the Invention
The present invention relates to a semiconductor device, which includes, in order to protect a semiconductor integrated circuit (hereinafter referred to as “IC”) against destruction due to an electrostatic pulse generated by electrostatic discharge (hereinafter referred to as “ESD”), an ESD protection element formed between an external connection terminal and an internal circuit region, or between the external connection terminal and an output element.
2. Description of the Related Art
Hitherto, semiconductor devices represented by ICs include ESD protection elements, and so-called off transistors are known as the ESD protection elements. The off transistor is an N-type MOS transistor having a gate potential fixed to a ground potential (hereinafter referred to as “VSS”), and thus is in an off state as a steady state.
What is important for an ESD countermeasure is that, in order to prevent ESD destruction of an internal circuit element or an output element represented by a driver, a large amount of an electrostatic pulse as much as possible is taken by the off transistor to be discharged to the VSS. Thus, it is important that a parasitic resistance of the off transistor is reduced with respect to the VSS of the IC in order to cause a current to flow to the VSS, which is generated by an electrostatic pulse of ESD and may flow through the internal circuit element and the output element which are required to be protected against the ESD.
However, for example, when the IC is large in size, a distance from the VSS to the off transistor is increased and the influence of a parasitic resistance of a source of the off transistor becomes more conspicuous. As a result, the off transistor cannot sufficiently exhibit its performance and an electrostatic pulse originally supposed to be taken by the off transistor may be propagated to the internal circuit element or the output element, resulting in IC destruction by the ESD.
As an example of a measure for addressing this trouble, there is proposed a device configuration as described in Japanese Patent Application Laid-open No. 2009-49331. Specifically, the device configuration has a feature in that a parasitic-resistance magnitude relationship is given to a parasitic resistance from an external connection terminal to an ESD protection element and a parasitic resistance from the ESD protection element to an internal circuit element, to thereby allow the ESD protection element to take a large amount of an electrostatic pulse as much as possible.
Hitherto, power management ICs particularly represented by voltage detectors or voltage regulators have been developed aiming to attain high driving performance and high value added circuits. As a measure for attaining high driving performance, for example, there is employed such a configuration that an output element is arranged near a VSS, to thereby reduce a parasitic resistance of the output element. As a measure for obtaining high added value, for example, there is employed such a configuration that an internal circuit is formed through a related-art CMOS process to have a unique function.
However, in the former case, namely, for attaining high driving performance, there is a fear in that the parasitic resistance of the output element is reduced to be lower than that of an off transistor, with the result that an electrostatic pulse cannot be taken by the off transistor sufficiently, and is propagated to the output element to cause IC destruction.
Moreover, in the latter case, namely, for obtaining high added value, there is a fear in that a parasitic resistance of a source of the off transistor becomes more conspicuous because an IC is large in size and an external connection terminal is located away from a VSS of the IC, with the result that an electrostatic pulse cannot sufficiently be taken by the off transistor, and is propagated to the internal circuit element to cause IC destruction.